1. Field of the Invention
This invention relates generally to the dense packaging of electronic circuitry through the stacking of integrated circuit (IC) chips (aka microcircuits or die) and, more specifically, to a stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
2. Description of the Related Art
A publication titled xe2x80x9cThree-Dimensional Electronics Packagingxe2x80x9d was issued in November, 1993 by Tech Search International. It describes the 3-D packaging techniques offered by over thirty manufacturers. It includes a table comparing 23 types of packaging in terms of density, manufacturability, flexibility and affordability. The publication also refers to four types of 3-D stacking techniques, one of which is xe2x80x9cbare die stackingxe2x80x9d. It then divides xe2x80x9cbare die assembly into standard ICSxe2x80x9d and xe2x80x9ccustom ICsxe2x80x9d.
The assignee of this application, Irvine Sensors Corporation, has been a leader in developing high density packaging of IC chips, originally for use in focal plane modules, and then for use in a variety of computer functions, such as memory. In the publication cited in the preceding paragraph, Irvine Sensors is listed as a developer of xe2x80x9cbare die assembliesxe2x80x9d using xe2x80x9ccustom ICsxe2x80x9d.
Generally, stacking of IC chips has emphasized use of identical-area chips, each of which performs the same function. The resulting stack is a rectangular parallelepiped (or cube) having substantially planar outer surfaces. One or more of the outer surfaces is an access plane, reached by electrical leads from the IC circuitry of the stacked chips, in order to permit connection to external circuitry.
An early effort to provide a 3-D electronics stack combining different functions, different area electronic chips is illustrated by Kravitz et al., U.S. Pat. No. 3,370,203. That patent shows stacked xe2x80x9cframesxe2x80x9d having dimensions xe2x80x9csuch that integrated circuits which have slightly different dimensions can be mounted thereonxe2x80x9d, explaining that xe2x80x9cintegrated circuits from different sources of supply are often advantageously incorporated in a single modulexe2x80x9d.
Irvine Sensors"" experience with various stacking methods has evolved over time:
Silicon Die Stacking
Irvine Sensors was initially xe2x80x9cstacking siliconxe2x80x9d by (1) buying whole silicon wafers from a wafer manufacturer, (2) metalizing an upper surface of the wafer to connect each die""s bond pads to an edge that will later be formed when the die is diced from the wafer; (3) dicing stackable die from the metallized wafer; (4) stacking the stackable die to form die-stacks, and then (5) forming edge connections on one or more sides of each die stack. Irvine Sensors found it troublesome to make die stacks by stacking silicon die, however, for several reason.
First, it was difficult to buy whole wafers because the wafer manufacturers do not want to reveal their yield or expose their built-in test structures that would make it easier to reverse engineer their circuitry, because the manufacturers do not usually have an existing sales structure for selling whole wafers, and because the manufacturers were concerned about liability issues if the stacked product should come to include a defective die.
Second, it was sometimes difficult to form the edge connects on the die stacks because they must be made within the dicing streets that have grown continually narrower as dicing technologies have improved. For example, the typical dicing street may be 6 mils or less and the saw kerf may be about 1.5 mils with poor registration relative to the die. As a result, a die""s original metallization may be undesirably exposed to the edge and thereby make it troublesome to form further access plane metallization along that edge without shorting.
Third, the probability of having a defective die in any one die-stack increases dramatically on the basis of the number of wafers in the wafer stack.
Finally, silicon stacking inherently requires same sized or homogenous die sizes.
Neo-Die Stacking
As a result of the foregoing problems associated with silicon die stacking, Irvine Sensors developed new technology involved creating xe2x80x9cNeo-Wafersxe2x80x9d and then stacking xe2x80x9cNeo-Chipsxe2x80x9d diced from the Neo-Wafers.
Irvine Sensors has two patents that relate to xe2x80x9cNeo-Wafersxe2x80x9d and xe2x80x9cNeo-Chipsxe2x80x9d, i.e. U.S. Pat. No. 5,953,588 entitled xe2x80x9cSTACKABLE LAYERS CONTAINING ENCAPSULATED IC CHIPSxe2x80x9d and U.S. Pat. No. 6,072,234 entitled xe2x80x9cSTACK OF EQUAL LAYER NEO-CHIPS CONTAINING ENCAPSULATED IC CHIPS OF DIFFERENT SIZES.xe2x80x9d The content of these two patents are hereby incorporated by reference in their entirety.
As disclosed more fully in the foregoing patents, the inventors make a xe2x80x9cNeo-Waferxe2x80x9d by (1) buying bare die (preferably pre-tested or xe2x80x9cknown goodxe2x80x9d die); (2) arranging the bare die in a spaced arrangement within a wafer-shaped fixture; and then (3) pouring a potting material such as epoxy onto the bare die within the wafer-shaped fixture. The Neo-Wafers, after being removed from the fixture, are surface metalized and the potted die are cut from the Neo-Wafers to provide xe2x80x9cNeo-Chipsxe2x80x9d of equal area that are suitable for stacking. A significant benefit of Neo-Wafer and Neo-Chips is that know good die may be used and different sized and number of die may be incorporated into same sized Neo-Chips.
Neo-stacking offers significant improvements over silicon die stacking, but it also proved troublesome under certain market circumstances. In particular, it is often difficult to buy bare die because many manufacturers will only sell only packaged die.
When trying to buy bare DRAM die from a particular manufacturer, for example, it was discovered that the manufacturer would not sell bare DRAM die, but would sell the DRAM die already pre-tested and installed in plastic packages, i.e. as xe2x80x9cplastic encapsulated microcircuitsxe2x80x9d or PEMs. The existing stacking methodologies, however, do not address the stacking of die contained in a plastic encapsulated microcircuit.
There remains a need, therefore, for a stackable microcircuit layer formed from a plastic encapsulated microcircuit and a method of making the same.
In a first aspect, the invention may be regarded as a method of making a stackable microcircuit layer comprising the steps of: providing a plastic encapsulated microcircuit (PEM) that includes (a) a microcircuit having an active surface containing integrated circuitry and a bond pad, and (b) an encapsulant in contact with the microcircuit; and modifying the PEM to produce a modified PEM having a modified surface on which modified surface is exposed a conductive member that is electrically connected to the bond pad.
In a second aspect, the invention may be regarded as a method of making a stackable microcircuit layer comprising the steps of: providing a plastic encapsulated microcircuit (PEM) that includes: (a) a microcircuit having a bond pad, (b) a conductive lead assembly connected to the bond pad, and (c) a plastic body encapsulating the microcircuit, the bond pad, and at least part of the conductive lead assembly; and grinding a top surface of the PEM to remove a top portion of the plastic body along with at least part of the conductive lead assembly to leave a planar section that contains the microcircuit and the bond pad.
In a third aspect, the invention may be regarded as a method of making a stackable microcircuit layer comprising the steps of: providing a plastic encapsulated microcircuit (PEM) that includes (a) a microcircuit having an active surface containing integrated circuitry and a bond pad, (b) a wire bond connected to the bond pad, a lead frame, and a wire that connects the wire bond to the lead frame, and (d) a plastic body that encapsulates the known-good microcircuit, the wire bond, the wire, and at least a portion of the lead frame; grinding a surface of the PEM to remove the lead frame and the wire and form a modified PEM that contains the microcircuit, the bond pad, and the wire bond, the modified PEM having a modified surface on which modified surface is exposed the wire bond that is connected to the bond pad; and forming an electrical lead on the modified surface that leads from the wire bond to an edge of the modified PEM.
In a fourth aspect, the invention may be regarded as a stackable microcircuit layer comprising: (1) a modified section of a plastic encapsulated microcircuit (PEM) that originally contained (a) a known-good microcircuit having a bond pad, (b) a conductive lead assembly connected to the bond pad, and (c) a plastic body encapsulating the known-good microcircuit, the bond pad, and the conductive lead assembly, the modified section formed by removing a portion of the conductive lead assembly from the PEM; the modified section having a modified surface, the modified section containing the known-good microcircuit, the bond pad, and a remaining portion of the conductive lead assembly with an end thereof exposed on the modified surface; and (2) a reroute lead on the modified surface of the modified section to connect the exposed portion of the remaining portion of conductive lead assembly with an edge of the modified section.